1. Field of the Invention
The present invention relates to a semiconductor device having a multi-level wiring layer and a method of manufacturing a semiconductor device, including a step of forming a multi-level single-crystal wiring layer.
2. Description of the Related Art
Recently, in the main portion of a computer or a communication device, large-scale integrated circuits (LSI) in each of which a great number of transistors, resistors and the like are connected with each other to form electrical circuits, and are integrated on one chip, are frequently used. Therefore, the performance of the whole device depends greatly on the performance of each single LSI.
The achievement of the performance of a single LSI can be achieved by increasing the degree of integration, that is, the downsizing of the element. However, when an LSI is downsized, the wiring width or the thickness of its wiring layer is reduced, which results in lowering of the reliability of the wiring.
As the factors of lowering the reliability of the wiring, the electromigration phenomenon and the stressmigration phenomenon are considered. The following is an explanation of these phenomena in connection with the case of an Al wiring layer, as an example. The electromigration is a phenomenon where electrons flowing to the Al wiring layer collide with Al atoms to transfer them. In contrast, the stress migration is a phenomenon where Al atoms are transferred by a mechanical stress from other materials used in the LSI.
Wiring layers presently used are made of polycrystalline aluminum, and therefore a great number of crystal grain boundaries are present in the wiring layer. Each of the crystal grain boundaries is a collectivity of lattice defects and structurally instable, and therefore the diffusion coefficient of Al atoms in each crystal grain boundary is large.
In an electromigration in a polycrystal Al wiring, Al atoms are migrated at the same speed up to a crystal grain boundary; however the moving speed of the Al atoms is increased in the crystal grain boundary. In other words, the depletion of Al atoms occurs on the upstream side, with respect to the crystal boundary, of the Al atom flow, whereas the accumulation of Al atoms occurs on the downstream side. The depletion and accumulation of Al atoms cause the generation of disconnection and hillock, respectively.
In a stress migration in a polycrystal Al wiring, as a mechanical stress is applied to a polycrystal Al wiring layer, Al atoms start to move in the direction in which the stress is released. In the stress migration, Al atoms move easily particularly in a crystal grain boundary in the polycrystal Al wiring layer, and therefore Al atoms are depleted in the grain boundary, causing a disconnection in the polycrystal Al wiring layer.
In order to prevent the lowering of the reliability of a polycrystal Al wiring layer, it is considered that the orientation and grain size of Al in the Al wiring layer should be proposed. An Al crystal has a face-centered cubic structure, and its surface energy is smallest at (111) face. Therefore, when &lt;111&gt; high orientation with respect to a vertical axis of the substrate is achieved, there is a less chance for a (111) face, which has a small surface energy, to be positioned opposite to a surface which makes the wiring cross section smallest. Therefore, the slit-like disconnection due to the stress migration can be suppressed, thus improving the reliability of the Al wiring layer.
However, when an Al wiring layer is formed by a conventional sputtering method, the &lt;111&gt; axes of individual Al crystal grains are distributed by 10.degree. or more. With a high orientation of this level, it is difficult to assure the reliability of the Al wiring layer.
When the diameters of individual crystal grains in the Al wiring layer are increased, the number of crystal grain boundaries can be reduced, thus making it possible to improve the property of resisting to electromigration. However, with the conventional heat treatment method, all the Al crystal grains cannot be uniformly enlarged in size, and therefore small Al crystal grains remain in its Al wiring layer. As a result, a disconnection occurs near these small-size Al crystal grains.
In order to improve the electromigration resisting property or the stress migration resisting property, it is proposed that an Al wiring layer should be single-crystalized. It is generally known that no crystal grain boundaries are present in a single-crystal wiring layer and therefore such a single-crystal wiring layer has a very high reliability.
Examples of the conventional method of forming a monocrsytal wiring layer are a method in which crystals are epitaxially grown on a single-crystal substrate and a lateral epitaxial method in which single-crystal species are grown on an amorphous insulation film. However, a wiring layer of an LSI is formed mostly on an amorphous insulation material, and is not brought into direct contact with a single-crystal material which serves as crystal species. Consequently, it is very difficult to form a single-crystal wiring layer by use of the epitaxial method in an LSI manufacture step.
Under the above-described circumstances, the inventors of the present invention proposed, as a method of forming a single-crystal wiring layer of an LSI, a new single-crystal wiring layer forming method, in which a metal thin film is formed on a wiring groove, and then the metal thin film is flocculated and separated by heating the substrate so as to fill the groove with the metal and single-crystalize the metal at the same time, thus forming a single-crystal wiring layer in the wiring groove (U.S. Pat. No. 5,409,862). With this method, a single-crystal wiring layer can be easily formed even on an amorphous insulation film. Further, it was made clear from the examination of the single-crystal wiring layer thus formed, that it has a very high reliability.
However, in the case where the above-described method proposed by the inventors of the present invention is applied to the manufacture of a multi-level single-crystal wiring layer, for example, a two-level single-crystal wiring layer, the following problem arises.
In the case where the aspect ratio (the depth of connection hole/the diameter of opening) of the connection hole which connects the lower-level single-crystal wiring layer with the upper-level single-crystal wiring layer, exceeds 1, a void is generated in the connection hole even if the upper-level single-crystal wiring layer is formed by the above-described method proposed by the same inventors.
Further, when the upper-level wiring layer is single-crystalized by heating the substrate, the lower-level wiring layer is expanded in volume, deforming the lower-level wiring layer or causing a disconnection in the layer.
As described above, the single-crystalization method of wiring was proposed by the same inventor as the method to improve the electromigration resisting property or the stress migration resisting property. However, in the case where this method is applied to a multilevel wiring layer having a lower-level wiring layer made of a polycrystal metal, an upper-level wiring layer can be single-crystalized; however the lower-level wiring layer is deformed.
Further, in both cases of the polycrsytal wiring layer and the single-crystal wiring layer, the wiring layer is thinned along with time, thus raising the wiring resistance gradually as compared to the designed value thereof.